The fundamentals of the MRI experiment are well known. Briefly (and hopefully without undue oversimplification), in a typical MRI system an object 10 (see FIG. 2) to be imaged (e.g., a portion of the human body) is placed in an external static magnetic field gradient. Protons within the object tend to align their spins in accordance with the magnetic field direction. The object is excited by one or more RF excitation pulses of appropriate frequency, timings and durations (as one example, so-called "spin-echo" type pulse sequences may be used). The RF excitation pulses generated at the Larmour frequency cause the protons to precess their spins. When each RF pulse is switched off, the nuclei precess back toward their equilibrium position and in this relaxation process emit an NMR response that can be detected by an RF receiver.
As is well known, different pulse sequences can be used to obtain different results. A pulse sequence generator (hereafter "sequencer") portion of the NMR system (e.g., often a high-speed hardware state machine based on a bit slice processor architecture) provides the sequence of control signals that controls the operation of the RF transmitter(s), RF receiver(s) and gradient magnet(s). The sequencer must reliably provide a high degree of flexibility (e.g., to provide generation of different desired pulse sequences) as well as adequate time resolution and other important features.
Briefly, a sequencer often comprises a microcoded sequential state machine, with each different state providing different output control signals to control different portions of the NMR equipment (e.g., RF transmitter and receiver, gradient coils, etc.). The "next state" to which the sequencer transitions is typically determined by the sequencer previous state. The time at which the transition occurs is generally variable (since different NMR equipment "states" last for different durations within a typical NMR pulse sequence) and may also be determined by the previous state. Different microcode may by loaded into a writable control store (WCS) within the sequencer to define different pulse sequences.
The following is a non-exhaustive listing of possibly representative prior patents and articles relating to NMR sequencers:
Hoenninger III U.S. Pat. No. 4,707,661 (1987);
Clark, "Pulsed Nuclear Resonance Apparatus," Review of Scientific Instruments, Vol 35, No 3, p316, March 1964;
Dick, "A Pulse Programmer for High-Power Nuclear Resonance," Journal of Physics E: Scientific Instruments, Vol 9, p1054, 1976;
Conway et al, "Circuit for A Digital Pulse Programmer," Rev. Sci. Instrum., Vol 48, No 6, p656, June 1977;
Caron, "A New Programmable Timer Designed for Pulsed NMR," Journal of Magnetic Resonance, Vol 31, p357, 1978;
Case et al, "Versatile Pulse Sequence Generator for Pulse NMR," Journal of Magnetic Resonance, Vol 35, p439, 1979;
Dart, "Highly Flexible Pulse Programmer for NMR Applications," Rev. Sci. Instrum., Vol 51. No 2, p224, February 1980;
Thomann et al, "Digital Pulse Programmer for An Electron-spin-resonance Computer-controlled Pulsed Spectrometer," Rev. Sci. Instrum., Vol 55, No 3, p389, March 1984;
Jensen et al, "A Universal Pulse Programmer for NMR Imaging," Proceedings for the Third Annual SMRM, p379, 1984;
Sidky et al, "State-machine Digital Pulse Generator," Rev. Sci. Instrum., Vol 59, No 5, p806, May 1988; and
Wachter et al, "Enhanced State-machine Pulse Programmer for Very-high-precision Pulse Programming," Rev. Sci. Instrum., Vol 59, No 10, p2285, October 1988.
The Hoenninger patent describes a microcoded sequencer having a 96-bit microcode format including an op code and associated branch address, a time duration, and various control fields. See also the Sidky et al, Caron et al, Wachter et al and Dart et al articles.
Such MRI microcoded sequencers generally include a writable control store (WCS) containing a sequence of microinstructions that define a corresponding sequence of machine states. The microinstructions are, in one sense, a computer program executed by the sequencer. This microcode computer program specifies sequencer outputs (e.g., to control portions of the MRI system such as the RF transmitter, the gradient coils, etc.) and also specifies the duration of such sequencer outputs. In addition, the microcode computer program specifies an ordered sequence of sequencer machine states--by providing a corresponding ordered "in line" sequence of microinstructions executed one after another in the order in which the microinstructions are stored in the control store and/or by providing conditional or unconditional "branching" microinstructions which cause particular microinstruction(s) to be performed in an order different from the order in which the microinstructions are stored in the control store.
Since the sequencer control store is writable (e.g., by a host computer linked to the sequencer), different NMR pulse sequences can be specified by simply downloading different microinstructions into the sequencer control store. Thus, different microinstruction sequences corresponding to hundreds of different NMR pulse sequences may be maintained on the host computer's mass storage (e.g., hard disk). Software executing on the host computer permits an operator to select (or create) particular sequencer microcode routines corresponding to particular experiments. The host computer then downloads the selected routines into the sequencer writable control store for execution by the sequencer. The host computer may download, along with the actual microcode routines, additional routines and data (e.g, commonly used subroutines, reference tables and the like) that must be present in the writable control store in order for the selected microcode routines to run.
A problem that has arisen in this type of microcoded sequencer arrangement relates to the size of the writable control store.
The microcode routines corresponding to many widely used simple NMR pulse sequences are relatively short and can easily be stored within a relatively small writable control store. Unfortunately, many useful experiments require more complex and lengthy NMR sequences--thus mandating much more lengthy microcode routines. It is not unusual for a single NMR experiment to require microcode routines having more than 32,000 microinstructions. There are also tendencies toward (a) increasing the width of the microinstructions (e.g., to on the order of 144 bits or more), and (b) increasing the time resolution of the sequencer (e.g., to on the order of 250 ns in order provide more precise control and timing parameters). These constraints require the sequencer writable control store to be extremely fast (e.g., on the order of 100 ns) and also very "wide". The width constraint forecloses the possibility of using standard memory chips in standard configurations, and instead requires multiple chips to be addressed in parallel in order to provide required widths. These various constraints together cause the memory and associated addressing components for the writable control store to represent a significant part of the cost of the NMR sequencer.
Thus, while recent significant advances in high density memory VLSI integrated circuits have allowed much larger memories to be used cost-effectively in many digital processing applications (such as general purpose digital computers), the critical timing and micro-instruction width constraints (as well as hardware complexity and reliability factors) imposed by modern NMR microcoded sequencer designs make it very important to keep the size of the sequencer writable control store relatively small.
Of course, memory paging and bank switching have long been used in general purpose digital computing environments to increase the effective size of a limited memory space.
Memory bank switching is commonly used to increase the effective size of a processor address space. See, for example, H. Al-Riahi, "Software-controlled Memory Duplication", 2407 Microprocessors and Microsystems No. 1, 9 (Jan/Feb. 1985) for an example of one such memory bank switching arrangement providing two alternate 64K memory banks and a capability to select between the two banks under software control. Such bank switching techniques do not solve the problems discussed above, however, since they do not reduce (and instead actually increase) the absolute amount of memory required.
Memory paging techniques do, however, serve to decrease the size of the memory required. "Page swapping" and associated "virtual storage" techniques were first devised in the 1960's in connection with the design of the some of the first multi-user operating systems. Virtual storage describes a technique wherein a particular user or application is assigned a much smaller portion of physical memory than he actually needs. The following is a simplified description of page swapping and virtual storage as implemented on a wide variety of computer systems since the 1960's.
Suppose, as a simple illustrative example, that a user compiles his application program to generate object code occupying 9K of memory but that the time-shared general purpose digital computer the user wishes to use to execute his program allocates the user only 4K of physical storage. The disparity between actual program size and allocated physical storage size is hidden from the user by page swapping services provided by the computer operating system. To run the user's 9K program, the operating system loads the first 4K (or less) of the user's program from mass storage into the limited physical memory block allocated to the user. The operating system causes the memory resident portion to be executed until a call is generated to an instruction not resident in memory. This call is intercepted by the operating system, which treats the call as a request for a page swap. The operating system "swaps" some or all of the memory resident code out of the physical memory allocated to the user and "swaps" in to physical memory a different portion of the user's object code containing the required instruction. Many such page swaps may be required before the program finishes executing--with the number of swaps needed depending upon the length of the program relative to the amount of physical memory available (and also upon the number and nature of internal branches within the program).
Page swapping, of course, represents a tradeoff between physical memory allocation and processing time. One of the problems with page swapping relates to the time and other processing overhead required to perform the swapping of pages into and out of memory. Much effort has been devoted to optimizing page swapping (e.g., by providing multiple smaller pages that can be swapped out independently, and by keeping memory resident certain sections of code that the operating system determines have a high probability of being needed).
Page swapping and virtual memory management thus permits large programs to be executed within much smaller physical memory spaces. Such page swapping techniques are provided in most modern multi-user systems, and have also become widely used in modern single-user systems such as personal computers and other microcomputers.
Prior art NMR systems were provided with an "on the fly" reloading technique somewhat analogous to page swapping. FIG. 1 is a graphical illustration in flowchart form of an exemplary prior art NMR system provided with such an "on the fly" writable control store reload capability. At block A (before the sequencer is started), the host computer loads the entire control store with micro-instructions. When the sequencer is started (blocks B and C), the sequencer repetitively reads from the control store and executes the micro-instructions stored within the store--thus generating NMR pulse sequences for a desired NMR experiment.
In many b useful NMR experiments, the sequencer might never (depending upon the size of the writable control store and the efficiency of the microcode) reach the end of the control store. However, in more complex experiments the sequencer will reach the end of the control store before the experiment has terminated ("Y" exit of decision block C) and require a micro-instruction that is not resident in the store. When the sequencer reaches the end of the control store, it suspends operations momentarily (block D) and requests the host to rewrite the control store (block E). The sequencer can be designed so that the host can very rapidly load the writable control store (e.g., using direct memory access (DMA) techniques). Rewriting the control store at block E may thus introduce only a few seconds of delay. Once the host has successfully rewritten the sequencer control store, the sequencer may resume operations at the beginning of the control store (or at some other predetermined transfer point) (block F). The writable control store can be reloaded as many times as necessary to cause the sequencer to execute the entire control program.
While the prior art technique shown in FIGURE 1 is successful in permitting NMR programmers to write microcode sequences longer than the writable control store, this technique also generates some significant problems in the real time control context of an NMR sequencer.
The regular RF stimulations provided during MRI imaging cause the NMR-sensitive molecules within the body being imaged to enter a dynamic steady state different from the unexcited steady state. If these regular stimulations are interrupted, relaxation causes the NMR-sensitive molecules to move away from the dynamic steady state toward their natural (unexcited) steady state. Interrupting the NMR pulse sequence to reload the writable control store interrupts the regular stimulations.
A technique known as "spin conditioning" has been used to stimulate the body back to dynamic steady state after such an interruption (and before data acquisition resumes). However, spin conditioning wastes time and may also not be entirely effective in avoiding image degradation caused by the interruption. This is due to the fact that the exponential time constants of the spins in some human body tissues are 1-2 seconds and spin conditioning is not usually performed for the 5-10 seconds required to return to steady state. There may also be eddy currents in the magnet with time constants in excess of 1 second. Since the time between reloads of the control store is constant in most cases, the disruption is periodic and the Fourier Transform of the resulting data is sensitive to this periodic perturbation of the data, resulting in image artifacts. A disruption near the zero phase encoding data acquisition will cause especially strong effects. Interruption due to control store loading should be avoided in order to prevent loss of steady state in the body which can lead to artifacts and noise in the acquired image data--and thus cause image degradation.
The present invention avoids such interruptions (and thus resulting image degradation) by providing a technique whereby the writable control store can be loaded while the sequencer is reading from the store.
Briefly, the present invention provides a microcoded sequencer for real time control of an NMR system, the sequencer including a control store which is "continually" loadable. Micro-instructions are loaded into a control store, and the sequencer executes micro-instructions out of this control store. Means are provided to ensure that the sequencer never executes micro-instructions from a section of the store currently being loaded, and also ensures (through timing features) that the sequencer can never, over time, execute micro-instructions more rapidly than new micro-instructions can be loaded (i.e., so that the sequencer never "runs out of" micro-instructions).
The present invention provides an arrangement wherein a host processor can access only (a) particular memory spaces of the control store (b) over particular time durations--with the particular memory spaces and the particular time durations each being specified (and limited) by the sequencer. The spatial limitation ensures that the sequencer never attempts to execute micro-instructions from a memory space within the control store that is currently being loaded by the host processor. The time limitation allows the same sequencer memory addressing and other hardware arrangements to be used by both the host processor and by the sequencer for control store access.
The spatial limitation feature described above is provided in the preferred embodiment by dividing the control store into two pages (both simultaneously within the sequencer address)--and by preventing the host processor from reloading the page storing micro-instructions the sequencer is currently executing. The sequencer is capable of executing only one micro-instruction at a time--and therefore can never execute micro-instructions from two pages simultaneously. The host processor may be appropriately programmed so that it never attempts to reload the page currently being accessed by the sequencer. The preferred embodiment sequencer design preferably includes spatial arbitration arrangements which sense an error condition whenever the host attempts to corrupt the page the sequencer is executing from.
In addition, the microcode is preferably organized such that each page contains all of the data, subroutines, and the like needed to execute each of the micro-instructions within that page. Thus, in the preferred embodiment, subroutines may preferably be loaded redundantly into each of the two pages so as to minimize branching between the two pages of the control store. In addition, the microcode is preferably generated to avoid recursion and iteration over page boundaries (e.g., by converting iterative routines larger than a single page into "in-line" code for loading into successive pages). A virtual sequencer control store of infinite length may thus be provided using a relatively small (e.g., 32K micro-instructions long) physical control store.
The reload timing considerations mentioned above are perhaps unique to the real time NMR experiment control functions performed by an NMR microcoded pulse sequencer. Unlike in most other contexts and environments, the short micro-instruction cycle times provided by an NMR pulse sequencer are not generally taken advantage of to provide higher micro-instruction throughput. Because of this special and unusual feature of the NMR system, leftover time between the end of a sequencer micro-instruction cycle for a particular micro-instruction and the end of the machine state caused by that micro-instruction is often considerable (e.g., on the order of milliseconds). In accordance with one important aspect of the present invention, this leftover time is used to reload the sequencer control store.
In somewhat more detail, the point in time at which a micro-instruction is executed by an NMR pulse sequencer determines the beginning of an associated NMR output state. The accuracy of the NMR experiment often critically depends upon when such output states begin with respect to one another. It is therefore highly desirable to provide an extremely short minimum micro-instruction cycle time (e.g., on the order of 250 ns)--and thus to provide sufficiently precise time resolution specifying the points in time when the NMR system is to transition to a new output state. This micro-instruction cycle time is typically far too short to subdivide into different time slices reserved for memory access by the sequencer and by the downloading host processor, respectively--and in the preferred embodiment such time divisions of a single micro-instruction cycle minimum duration are avoided entirely.
However, unlike most general purpose digital computers (in which instruction cycle times are almost always on the same order as machine state durations), the duration of a typical state of a microcoded NMR sequencer is typically much longer than, for example, a 250 ns minimum micro-instruction cycle duration. For example, the exemplary preferred embodiment sequencer is capable of encoding a state duration of up to eight seconds --with a begin/end time resolution of 250 ns. Typical NMR sequencer state durations will be on the order of milliseconds or tenths of seconds, and state durations on the same order as micro-instruction cycle durations will be programmed only rarely.
In the preferred embodiment, the sequencer memory cycle time is much faster than the host bus cycle time. The preferred embodiment takes advantage of this sequencer speed advantage by permitting the host processor to address and write directly into the sequencer control store with no significant buffering (thus reducing hardware cost and complexity). If the host processor attempts to write into the sequencer control store during a time period in which the sequencer also needs access, the sequencer takes priority and causes the host processor to wait (in the preferred embodiment, this host processor "wait" simply causes the host processor bus cycle time to be extended).
It is possible that the sequencer may execute a series of single clock cycle state changes--thus preventing the host bus cycle from completing (i.e., causing the host processor bus cycle to exceed a certain maximum time and thus "time out"). In the preferred embodiment, the sequencer micro-instruction cycle time is 250 ns and the host processor (DIGITAL, INC. Q22) bus timeout period is 10 ns. There can thus be 39 successive 250 ns duration sequencer micro-instructions in the preferred exemplary implementation before the host processor bus times out. Very few such 250 ns micro-instructions are consecutively executed during normal NMR pulse sequence generation, so this is not a problem encountered in normal system operation.
Moreover, in accordance with the preferred embodiment of the present invention, the sequencer performs most or all of the processing for a micro-instruction within the first 250 ns after a state transition occurs. If the state duration selected by the processed micro-instruction is only 250 ns long (as it will be occasionally during normal operation), the sequencer changes to the next state at the end of the 250 ns minimum micro-instruction cycle time--leaving no "leftover" time for reloading the control store. However, if the state duration specified by the processed micro-instruction is longer than the 250 ns minimum cycle time, the sequencer permits the host processor to access and reload the control store for the remainder of the state duration (until just immediately prior to state termination).
And in the preferred embodiment, a host-to-sequencer write can be completed within a single sequencer (minimum) micro-instruction cycle time (i.e., 250 ns)--so that a write that has begun is always guaranteed to end prior to the time the sequencer must next change states. Moreover, this rapid completion of a host data write cycle in the preferred embodiment prevents host bus timeout from occurring whenever there is even a single "free" sequencer micro-instruction cycle during the host bus timeout period.
Thus, it is possible over a short time for successive short machine states to occur such that the host is prevented from reloading the control store more rapidly than the sequencer executes micro-instructions from the store. However, this situation is highly unlikely to exist for a significant time period during actual operation of the NMR system due to the relatively long durations of useful NMR pulse output sequences and associated sequencer states. Because the nature of the NMR experiment constrains the preferred embodiment pulse sequencer to always process micro-instructions far less rapidly than it is actually capable of processing them, the average sequencer state duration far exceeds the average time it takes for the host to reload a micro-instruction--and thus there is always enough time left over during practical NMR system operation to reload the control store with micro-instructions before the sequencer "runs out of" micro-instructions to execute.
The loading of the sequencer microcode control store when the sequencer is running in accordance with the present invention ensures that the sequencer outputs are not interrupted even though the control store is not large enough to store all of the microcode needed to execute an MRI sequence. There are other advantages provided by continuous loading, including reduction of latency between the issue of a sequence "link and load" command to the host processor and the actual beginning of execution (since only a small portion of the microcode needs to be linked and loaded before the sequencer can be started).
Since the preferred embodiment host processor and the microcode sequencer provide for continual loading of the sequencer control store while the sequencer is running, the user/programmer may view the control store as an ideal virtual control store having an unlimited size. Programmers may now write NMR microcode sequences without concern for whether they will "fit" into the physical memory space provided by the NMR sequencer control store. In addition, reloading of the control store is completely transparent to ongoing NMR pulse sequences in the preferred embodiment and causes no troublesome interruption of such sequences.